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[ak4528] ms0011-e-02 2012/01 - 1 - general description the ak4528 is a high performance 24bit codec for the 96khz recording sy stem. the adc has an enhanced dual bit architecture with wide dynamic range. the dac uses the new developed advanced multi bit architecture and achieves low outband noise and high jitter tolerance by use of scf (switched capacitor filter) techniques. features ? 24bit 2ch adc - 64x oversampling - full differential inputs - s/(n+d): 94db - dynamic range, s/n: 108db - digital hpf for offset cancellation - i/f format: msb justified or i 2 s ? 24bit 2ch dac - 128x oversampling - 24bit 8 times digital filter ripple: 0.005db, attenuation: 75db - scf - differential outputs - s/(n+d): 94db - dynamic range, s/n: 110db - de-emphasis for 32khz, 44.1khz and 48khz sampling - output datt with ?72db att - soft mute - i/f format: msb justified, lsb justified or i 2 s ? high jitter tolerance ? 3-wire serial interface for volume control ? master clock - 256fs/384fs/512fs/768fs/1024fs ? 5v operation ? 3v power supply pin for 3v i/f ? small 28pin ssop package high performance 24bit 96khz audio codec ak4528
[ak4528] ms0011-e-02 2012/01 - 2 - ? block diagram a inl+ a inr+ vcom a outl+ a outl- a outr- a outr+ vref va a gnd csn (dif) cclk (cks1) cdti (cks0) p/s mclk sdti sdto bick lrck dgnd vt vd a dc dac hpf datt smute a udio i/f controller control register i/f clock divider pdn a inl- a inr- dem1 dem0 dfs block diagram x compatibility of ak4528 with ak4524 function ak4528 ak4524 adc s/(n+d) 94db 90db adc dr, s/n 108db 100db input pga & att x o adc inputs differential inputs single-end inputs master mode x o x?tal oscillating circuit x o quad speed mode x o parallel mode o x o: available, x: not available
[ak4528] ms0011-e-02 2012/01 - 3 - ? ordering guide AK4528VM 40 a +85 q c 28pin ssop (0.65mm pitch) ? pin layout agnd vcom ainr+ ainr- ainl+ ainl- vref va p/s mclk lrck bick sdto sdti cdti(cks0) cclk(cks1) csn(dif) dfs dem1 vt vd dgnd aoutl- aoutl+ aoutr- aoutr+ pdn dem0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ak4528 top view
[ak4528] ms0011-e-02 2012/01 - 4 - pin/function no. pin name i/o function 1 vcom o common voltage output pin, va/2 bias voltage of adc inputs and dac outputs. 2 ainr+ i rch positive input pin 3 ainr ? i rch negative input pin 4 ainl+ i lch positive input pin 5 ainl ? i lch negative input pin 6 vref i voltage reference input pin, va used as a voltage reference by adc & dac. vref is connected externally to filtered va. 7 agnd - analog ground pin 8 va - analog power supply pin, 4.75 5.25v 9 p/s i parallel/serial mode select pin ?l?: serial mode, ?h?: parallel mode 10 mclk i master clock input pin 11 lrck i input/output channel clock pin 12 bick i audio serial data clock pin 13 sdto o audio serial data output pin 14 sdti i audio serial data input pin cdti i control data input pin in serial mode 15 cks0 i master clock select pin cclk i control data clock pin in serial mode 16 cks1 i master clock select pin csn i chip select pi n in serial mode 17 dif i digital audio interface select pin ?l?: 24bit msb justified, ?h?: i 2 s compatible 18 dfs i double speed sampling mode pin 19 pdn i power-down mode pin ?h?: power up, ?l?: power down reset and initialize the control register. 20 dem0 i de-emphasis control pin 21 dem1 i de-emphasis control pin 22 vt - output buffer power supply pin, 2.7 5.25v 23 vd - digital power supply pin, 4.75 5.25v 24 dgnd - digital ground pin 25 aoutl ? o lch negative analog output pin 26 aoutl+ o lch positive analog output pin 27 aoutr ? o rch negative analog output pin 28 aoutr+ o rch positive analog output pin note: all input pins should not be left floating.
[ak4528] ms0011-e-02 2012/01 - 5 - absolute maximum ratings (agnd, dgnd=0v; note 1) parameter symbol min max unit power supplies: analog digital output buffer vd ? va va vd vt vda ? 0.3 ? 0.3 ? 0.3 - 6.0 6.0 6.0 0.3 v v v v input current, any pin except supplies iin - 10 ma analog input voltage vina ? 0.3 va+0.3 v digital input voltage vind ? 0.3 va+0.3 v ambient temperature (powered applied) ta ? 40 85 c storage temperature tstg ? 65 150 c note: 1. all voltages with respect to ground. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (agnd, dgnd=0v; note 1) parameter symbol min typ max unit power supplies analog digital output buffer va vd vt 4.75 4.75 2.7 5.0 5.0 3.0 5.25 va vd v v v voltage reference vref 3.0 - va v note: 1. all voltages with respect to ground. 2. va and vd should be powered at the same time or va should be powered earlier than vd. the power up sequence between va and vt, or vd and vt is not critical. *akm assumes no responsibility for the usage beyond the conditions in this datasheet.
[ak4528] ms0011-e-02 2012/01 - 6 - analog characteristics (ta=25 c; va, vd, vt=5.0v; agnd=dgnd=0v; vref=va; fs= 44.1khz; signal frequency =1khz; 24bit data; measurement frequency = 20hz 20khz at fs=44.1khz, 40hz 40khz at fs=96khz; unless otherwise specified) parameter min typ max unit input pga characteristics: adc analog input characteristics: analog source impedance = 330 resolution 24 bits input voltage (note 3) 2.6 2.8 3.0 vpp input resistance fs=44.1khz fs=96khz 16 7 27 12 k k s/(n+d) ( ? 0.5dbfs) fs=44.1khz fs=96khz 88 84 94 92 db db dr ( ? 60dbfs) fs=44.1khz, a-weighted fs=96khz 100 95 108 103 db db s/n fs=44.1khz, a-weighted fs=96khz 100 95 108 103 db db interchannel isolation 90 110 db interchannel gain mismatch 0.2 0.5 db gain drift 20 - ppm/ c input voltage (note 3) 2.6 2.8 3.0 vpp input resistance fs=44.1khz fs=96khz 16 7 27 12 k k input dc bias voltage (note 4) 0.56va - 0.60va v power supply rejection (note 5) - 50 - db dac analog output characteristics: resolution 24 bits s/(n+d) (0dbfs) fs=44.1khz fs=96khz 88 85 94 93 db db dr ( ? 60dbfs) fs=44.1khz, a-weighted fs=96khz 104 96 110 104 db db s/n fs=44.1khz, a-weighted fs=96khz 104 96 110 104 db db interchannel isolation 90 110 db interchannel gain mismatch 0.2 0.5 db gain drift 20 - ppm/ c output voltage (note 6) 5.0 5.4 5.8 vpp load resistance (in case of ac load) 1 k output current 1.5 ma load capacitance 25 pf power supply rejection (note 5) 50 - db note: 3. this voltage is input to ain+ and ain ? pin, and is proportional to vref. vin = 0.56 x vref. 4. measured by figure 12. dc bias voltage, vb = 4.7k / (3.3k + 4.7k) x va = 0.5875va. 5. psr is applied to va, vd, vt with 1khz, 50mvpp. vref pin is held a constant voltage. 6. full scale (0db) of the output volta ge when summing the differential outputs, aout+/ ? by unity gain. this voltage is proportional to vref. vout=1.08 x vref x gain.
[ak4528] ms0011-e-02 2012/01 - 7 - parameter min typ max unit power supplies power supply current normal operation (pdn=?h?) va vd+vt (fs=44.1khz) (fs=96khz) power-down mode (pdn=?l?) (note 7) va vd+vt 38 10 18 10 10 57 20 36 100 100 ma ma ma a a note: 7. all digital input pins are held vd or dgnd. filter characteristics (ta=25 c; va, vd=4.75 5.25v; vt=2.7 5.25v; fs=44.1khz; dem=off) parameter symbol min typ max unit adc digital filter (decimation lpf): passband (note 8) ? 0.005db ? 0.02db ? 0.06db ? 6.0db pb 0 - - - 20.02 20.20 22.05 19.76 - - - khz khz khz khz stopband sb 24.34 khz passband ripple pr 0.005 db stopband attenuation sa 80 db group delay (note 9) gd 31 1/fs group delay distortion gd 0 s adc digital filter (hpf): frequency response (note 8) ? 3db ? 0.5db ? 0.1db fr 0.9 2.7 6.0 hz hz hz dac digital filter: passband (note 8) ? 0.01db ? 6.0db pb 0 - 22.05 20.0 - khz khz stopband sb 24.1 khz passband ripple pr 0.005 db stopband attenuation sa 75 db group delay (note 9) gd 30 1/fs dac digital filter + scf: frequency response: 0 20.0khz 40khz (note 10) fr 0.2 0.3 db db note: 8. the passband and stopband frequencies scale with fs. for example, 20.02khz at -0.02db is 0.454 x fs. the reference frequency of these responses is 1khz. 9. the calculating delay time which occurred by digital filtering. this time is fro m the input of analog signal to setting the 24bit data of both channels to the output register for adc. for dac, this time is from setting the 24bit data of both channels on input register to the output of analog signal. 10. fs=96khz.
[ak4528] ms0011-e-02 2012/01 - 8 - dc characteristics (ta=25 c; va, vd=4.75 5.25v; vt=2.7 5.25v) parameter symbol min typ max unit high-level input voltage low-level input voltage vih vil 2.2 - - - - 0.8 v v high-level output voltage (iout= ? 100 a) (note 11) low-level output voltage (iout=100 a) voh vol 2.7 / vt ? 0.5 - - - - 0.5 v v input leakage current iin - - 10 a note: 11. the min value is lower voltage of 2.7v or vt ? 0.5v. switching characteristics (ta=25 c; va, vd=4.75 5.25v, vt=2.7 5.25v; c l =20pf) parameter symbol min typ max unit master clock timing frequency pulse width low pulse width high fclk tclkl tclkh 7.68 0.4/fclk 0.4/fclk 55.296 mhz ns ns lrck frequency normal speed mode (dfs = ?0?) double speed mode (dfs = ?1?) duty cycle fsn fsd duty 30 60 45 44.1 88.2 54 108 55 khz khz % audio interface timing bick period bick pulse width low pulse width high lrck edge to bick ? ? (note 12) bick ? ? to lrck edge (note 12) lrck to sdto (msb) (except i 2 s mode) bick ? ? to sdto sdti hold time sdti setup time tbck tbckl tbckh tlrb tblr tlrs tbsd tsdh tsds 81 33 33 20 20 20 20 40 40 ns ns ns ns ns ns ns ns ns note 12. bick rising edge must not occur at the same time as lrck edge.
[ak4528] ms0011-e-02 2012/01 - 9 - parameter symbol min typ max unit control interface timing (p/s=?l?) cclk period cclk pulse width low pulse width high cdti setup time cdti hold time csn ?h? time csn ?l? time csn ? ? to cclk ? ? cclk ? ? to csn ? ? tcck tcckl tcckh tcds tcdh tcsw tcsw tcss tcsh 200 80 80 40 40 150 150 150 50 ns ns ns ns ns ns ns ns ns reset timing pdn pulse width (note 13) rstadn ? ? to sdto valid (note 14) pdn ? ? to sdto valid (note 15) tpd tpdv tpdv 150 516 516 ns 1/fs 1/fs note: 13. the ak4528 can be reset by bringing pdn ?l?. 14. in serial mode, these cycl es are the number of lrck rising from rstadn bit. 15. in parallel mode, these cycles are the number of lrck rising from pdn pin. ? timing diagram 1/fclk tclkl vil tclkh mclk vih 1/fs lrck vih vil tbck tbckl vih tbckh bick vil clock timing
[ak4528] ms0011-e-02 2012/01 - 10 - lrck bick sdto sdti tblr tlrb tlrs tbsd tsds tsdh vih vil vih vil 50%vt vih vil audio interface timing csn cclk cdti tcss tcckl tcckh tcds tcdh c1 c0 r/w a 4 vih vil vih vil vih vil write command input timing csn cclk cdti tcsw tcsh d3 d2 d1 d0 vih vil vih vil vih vil write data input timing tpd vil pdn power down & reset timing
[ak4528] ms0011-e-02 2012/01 - 11 - operation overview ? system clock input the external clocks, which are required to ak4528, are mclk, bick and lrck. mclk should be synchronized with lrck but the phase is not critical. the frequency of mclk is set by cmode, cks0-1 and dfs bits in serial mode, or by cks0-1, dfs pins in parallel mode (see table 2 and 3) . the cks0-1 and dfs pin should be changed during the pdn pin = ?l?. the cmode, cks0-1 and dfs bits are changed during rstadn = rstdan = ?0?. external clocks (mclk, bick and lrck) should always be present whenever the ak4528 is in normal operation mode (pdn = ?h? and at least one of adc and dac is in norma l operation mode). if these clocks are not provided, the ak4528 may draw excess current because the device utilizes dynamic refreshed logic in ternally. if the external clocks are not present, the ak4528 should be in the power-down mode (pdn = ?l? or set both adc and dac power down mode by the register). cmode bit cks1 bit cks0 bit mclk normal speed (dfs bit = ?0?) mclk double speed (dfs bit = ?1?) 0 0 0 256fs n/a 0 0 1 512fs 256fs 0 1 0 1024fs 512fs 1 0 0 384fs n/a 1 0 1 768fs 384fs default table 1. master clock frequency select in serial mode cks1 pin cks0 pin mclk normal speed (dfs pin = ?l?) mclk double speed (dfs pin = ?h?) l l 256fs n/a l h 512fs 256fs h l 384fs n/a h h 1024fs 512fs table 2. master clock frequency select in parallel mode mclk normal speed (dfs = ?0?) fs=44.1khz fs=48khz mclk double speed (dfs = ?1?) fs=88.2khz fs=96khz 256fs 11.2896mhz 12.288mhz n/a n/a n/a 512fs 22.5792mhz 24.576mhz 256fs 22.5792mhz 24.576mhz 1024fs 45.1584mhz 49.152mhz 512fs 45.1584mhz 49.152mhz 384fs 16.9344mhz 18.432mhz n/a n/a n/a 768fs 33.8688mhz 36.864mhz 384fs 33.8688mhz 36.864mhz table 3. master clock frequencies example note. do not set any mode which is not described in table1-3.
[ak4528] ms0011-e-02 2012/01 - 12 - ? audio serial interface format in case of serial mode, the dif0-2 bits as shown in table 4 support five serial formats. in case of parallel mode, two formats (mode 2 and 3) are supported by dif pin (table 5). in all modes the serial data is msb-first, 2?s compliment format. the sdto is clocked out on the falling edge of bick and the sdti is latched on the rising edge. mode dif2 bit dif1 bit dif0 bit sdto sdti lrck bick 0 0 0 0 24bit, msb justified 16bit, lsb justified h/l t 32fs 1 0 0 1 24bit, msb justified 20bit, lsb justified h/l t 40fs 2 0 1 0 24bit, msb justified 24bit, msb justified h/l t 48fs 3 0 1 1 24bit, i 2 s 24bit, i 2 s l/h t 48fs 4 1 0 0 24bit, msb justified 24bit, lsb justified h/l t 48fs defaul t table 4. audio data format in serial mode mode dif pin sdto sdti lrck bick 2 0 24bit, msb justified 24bit, msb justified h/l t 48fs 3 1 24bit, i 2 s 24bit, i 2 s l/h t 48fs table 5. audio data format in parallel mode lrck bick ( 64fs ) sdto(o) 012 19 17 18 20 31 0 1 2 19 17 18 20 31 0 23 1 22 4 23 22 7 6 4 23 sdti ( i ) 1 14 0 12 11 1 14 0 12 11 sdto-19:msb, 0:lsb; sdti-15:msb, 0:lsb lch data rch data don?t care don?t care 76 bick(32fs) sdto ( o ) 0 1 2 9 10 12 13 15 0 1 2 9 10 12 13 15 0 23 1 22 12 23 22 12 15 14 23 sdti(i) 1 60 43 1 15 0 54 15 14 2 98 11 10 21 15 14 13 31114 13 5 7 21 5 3 13 15 30 21 33 21 14 13 7 6 3 2 15 14 11 8 9 10 11 13 5 3 15 13 2 2 figure 1. mode 0 timing lrck bick(64fs) sdto ( o ) 0 1 2 12 13 14 24 25 31 0 1 2 12 13 14 24 25 31 0 23 1 22 0 23 22 12 11 10 0 23 sdti(i) 1 18 0 19 8 7 1 18 0 19 8 7 sdto-23:msb, 0:lsb; sdti-19:msb, 0:lsb lch data rch data don?t care don?t care 12 11 10 figure 2. mode 1 timing
[ak4528] ms0011-e-02 2012/01 - 13 - lrck bick(64fs) sdto ( o ) 0 1 2 1819202122 0 1 2 181920 22 21 0 1 sdti(i) 23 24 25 23 24 25 23 22 4 23 22 5 4 5 4 1 22 0 23 3 2 1 22 0 23 3 2 23:msb, 0:lsb lch data rch data don?t care don?t care 5 54 10 32 10 32 23 figure 3. mode 2 timing lrck bick(64fs) sdto ( o ) 0 1 2 3 19 20 21 22 0 1 2 3 19 20 22 21 0 1 sdti(i) 23 24 25 23 24 25 23 22 4 23 22 5 4 5 4 1 22 0 23 3 2 1 22 0 23 3 2 23:msb, 0:lsb lch data rch data don?t care don?t care 5 54 10 32 10 32 figure 4. mode 3 timing lrck bick(64fs) sdto ( o ) 0 1 2 8 9 10 20 21 31 0 1 2 8 9 10 20 21 31 0 23 1 22 0 23 22 16 15 14 0 23 sdti(i) 1 22 0 23 12 11 1 22 0 23 12 11 23:msb, 0:lsb lch data rch data don?t care don?t care 16 15 14 figure 5. mode 4 timing
[ak4528] ms0011-e-02 2012/01 - 14 - ? parallel/serial mode control when p/s= ?h?, ak4528 is in parallel mode. the audio interface format is selected by dif pin, and dfs and ck0-1 pins select the frequency of mclk. when p/s= ?l?, ak4528 is in serial mode. the cks1, cks0 and dif pins are changed to cdti, cclk and csn pins respectively. the dem0-1 and dfs are ored between pin and register respectively, so those are able to control by pins even in serial mode. to control all the functi ons by register, set dem0-1 and dfs pins ?l?. ? digital high pass filter the adc has a digital high pass filter (hpf) for dc offset cancel. the cut-off frequency of the hpf is 0.9hz at fs=44.1khz and also scales with sa mpling rate (fs). this hpf can be off for each channel by register. ? output volume the ak4528 includes digital volumes (oatt) with 128 levels (including mute) in front of dac. the oatt is a pseudo-log volume linear-int erpolated internally. when the level is change d, the transition to new value takes 8031 levels (max) and is done by soft transition. th erefore, there is not any switching noise. ? de-emphasis filter the dac includes the digital de-emphasis filter (tc=50/15 p s) by iir filter. this filter supports to three frequencies (32khz, 44.1khz and 48khz). this setting is done by cont orl register and always off at double speed mode. no dem1 dem0 mode 0 0 0 44.1khz 1 0 1 off 2 1 0 48khz 3 1 1 32khz default in serial mode table 6. de-emphasis control (dfs=?0?)
[ak4528] ms0011-e-02 2012/01 - 15 - ? soft mute operation soft mute operation is performed at digital domain. when smute goes ?1?, the output signal is attenuated by f during 1024 lrck cycles. when smute is returned to ?0?, the mu te is cancelled and the output attenuation gradually changes to 0db during 1024 lrck cycles. if the soft mute is cancelled within 1024 lrck cycles after starting of the operation, the attenuation is discontinued and returned to 0db. soft mute function is independent to output volum e, and those two functions are cascade connected. smute a ttenuation 1024/fs 0db - f 1024/fs gd gd (1) (2) (3) notes: (1) the output signal is attenuated by f during 1024 lrck cycles (1024/fs). (2) analog output corresponding to digital input has the group delay (gd). (3) if the soft mute is cancelled within 1024 lrck cycles, the attenuation is discontinued and returned to 0db. figure 6. soft mute
[ak4528] ms0011-e-02 2012/01 - 16 - ? power down & reset the adc and dac of ak4528 are placed in the power-down mode by bringing a power down pin (pdn)=?l? and each digital filter is also reset at the same time. the internal register values are in itialized by pdn = ?l?. this reset should always be done after power-up. in case of serial mode, the default value of both control registers for adc and dac are in reset state (rstadn = rstdan = ?0?), each register sholud be cancelled after doi ng the needed setting. in case of the adc, an analog initialization cycle starts after exiting the power-down or reset state. therefore, the output data, sdto becomes available after 516 cycles of lrck. in case of dac, the initialization cy cle starts after pdn = ?h? or pwvr bit = ?1?. the power down mode can be also controlled by the registers (pwad, pwda). power supply rstadn(registe rstdan(registe pw ad(register) pw da(register) pw vr(register) a dc internal state sdto oatt a out dac internal state external mute example external clocks the clocks can be stopped. pd reset inita normal pd inita normal ?0? ?0? output output pd reset pd normal normal 00h 00h o xxh xxh 00h 00h o xxh xxh ?0? fi output fi mclk, lrck, bick pdn pin ** * initd * hi-z hi-z output pd normal 00h 00h o xxh xxh fi ** hi-z output pd ?0? 512/fs 512/fs initd x inita: initializing period of adc analog section (516/fs). x initd: initializing period of dac analog section (512/fs). x pd: power down state. in case of pdn = ?l?, the contents of all registers are initialized, otherwise hold. x xxh: the current value in att register. x fi: fade in. after exiting power down and reset state, att value fades in by 8032/fs cycles (max). x aout: some pop noise may occur at ?*?. figure 7. reset & power down sequence in serial mode
[ak4528] ms0011-e-02 2012/01 - 17 - in case of parallel mode, both adc and dac are powered up with releasing internal reset stat e when pdn is set to ?h?. therefore each outputs start to output at once. however the initialization of adc /dac, and the fade-in cycle of oatt (8031/fs) are exist. power supply a dc internal state sdto oatt a out dac internal state external mute example external clocks the clocks can be stopped. pd inita normal pd inita normal ?0? ?0? output output pd pd normal normal 00h 7fh 7fh 00h 00h 7fh 7fh hi-z hi-z fi output fi mclk, lrck, bick pdn pin ** 00h mclk, lrck, bick output * 512/fs 512/fs initd initd ? inita: initializing period of adc analog section (516/fs). ? initd: initializing period of dac analog section (512/fs). ? pd: power down state. ? fi: fade in. after exiting power down state, att value fades in by 8032/fs cycles. ? aout: some pop noise may occur at ?*?. figure 8. reset & power down sequence in parallel mode
[ak4528] ms0011-e-02 2012/01 - 18 - ? serial control interface the serial control interface is enabled by the p/s pin = ?l?. the internal registers are written by the 3-wire p p interface pins: csn, cclk, cdti. the data on this interface consists of chip address (2bits, fixed to c0/1 = ?01?) read/write (1bit, fixed to ?1?), register address (msb first, 5bits) and c ontrol data (msb first, 8bits). address and data is clocked in on the rising edge of cclk. data is latched after a low-to-high transition of csn. the maximum clock speed of the cclk is 5mhz. the csn should be ?h? if no access. the chip address is fixed to ?10?. writing is invalid for the access to the chip address except for ?10?. pdn = ?l? resets the registers to their default values. function parallel mode serial mode double speed o o de-emphasis o o smute x o output digital att x o hpf off x o mclk; 768fs@normal speed 384fs@double speed x o 16/20/24bit lsb justified format x o table 7. function list (o: available, x: not available) when pdn = ?l?, internal registers are initialized. in case of changing p/s pin, please set pdn = ?l? to reset the device. in case of serial mode, the internal timings are initialized by rstn = ?0?, but the contents of registers are hold. csn cclk 01 2 345 67891011 12 13 14 15 cdti c1 c0 a 2 a 3 a 1 a 0 a 4 d7d6d5d4d3d2d1d0 r/w c1-c0: chip address (fixed to ?10?) r/w: read/write (fixed to ?1?:write only) a 4-a0: register address d7-d0: control data figure 9. control i/f timing *ak4528 does not support the read. c1, c0 and r/w are fixed (?101?).
[ak4528] ms0011-e-02 2012/01 - 19 - ? register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power down control 0 0 0 0 0 pwvr pwad pwda 01h reset control te7 te6 te5 te4 0 0 rstadn rstdan 02h clock and format control dif2 dif1 dif0 cmode cks1 cks0 0 dfs 03h deem and volume control smute 0 0 0 hpfr hpfl dem1 dem0 04h lch att control 0 attl6 attl5 attl4 attl3 attl2 attl1 attl0 05h rch att control 0 attr6 a ttr5 attr4 attr3 attr2 attr1 attr0 note: for address from 06h to 1f h, data should not be written. in case of wr iting to 01h, write ?0000? to d7-4. pdn = ?l? resets the registers to their default values. ? control register setup sequence the setting of clock mode or data format by control register should be done during rstadn = rstdan = ?0?, and outputs of adc/dac should be muted. 1. in case of using pdn pin (1) set pdn= ?h?. (2) set registers for clock mode, data format, etc. (3) cancel the reset state by setting rstadn or rstdan to ?1?. refer to reset contorl register (01h). 2. in case of not using pdn pin (1) set rstadn = rstdan = ?0?. (2) set registers for clock mode, data format, etc. (3) cancel the reset state by setting rstadn or rstdan to ?1?. refer to reset contorl register (01h). note: those settings may generate pop noise. pleas e mute the output of adc and dac externally.
[ak4528] ms0011-e-02 2012/01 - 20 - ? register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power down control 0 0 0 0 0 pwvr pwad pwda default 0 0 0 0 0 1 1 1 pwda: dac power down 0: power down 1: power up only dac section is powered down by ?0? and then the aouts go hi-z immediately. the oatts also go ?00h?. but the contents of all register are not initialized and enabled to write to the registers. after exiting the power down mode, the oatts fade in the setting value of the control register (04h & 05h). the analog outputs should be muted externally as some pop noise may occur when entering to and exiting from this mode. pwad: adc power down 0: power down 1: power up only adc section is powered down by ?0? and then th e sdto goes ?l? immediately. the contents of all register are not initialized and enabled to write to the registers. after exiting the power down mode, adc outputs ?0? during first 516 lrck cycles. pwvr: vref power down 0: power down 1: power up all sections are powered down by ?0? and then both adc and dac do not operate. the contents of all register are not initialized and enabled to write to the registers. when pwad and pwda go ?0? and pwvr goes ?1?, only vref section can be powered up. addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h reset control te7 te6 te5 te4 0 0 rstadn rstdan default 0 0 0 0 0 0 0 0 te7-4: test control register enable must be fixed to ?0000?. rstdan: dac reset 0: reset 1: normal operation the internal timing is reset by ?0? and then the aouts go vcom voltage immedi ately. the oatts also go ?00h?. but the contents of all register are not in itialized and enabled to write to the registers. after exiting the power down mode, the oatts fade in the setting value of the control register (06h & 07h). the analog outputs should be mute d externally as some pop noise may o ccur when entering to and exiting from this mode. rstdan: adc reset 0: reset 1: normal operation the internal timing is reset by ?0? and then sdto goes ?l? immediately. but the cont ents of all register are not initialized and enabled to write to the register. after exiting the power down mode, adcs output ?0? during first 516 lrck cycles.
[ak4528] ms0011-e-02 2012/01 - 21 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h clock and format control dif2 dif1 dif0 cmode cks1 cks0 0 dfs default 0 1 0 0 0 0 0 0 dfs: sampling speed control (see table 1 and table 3) default : normal speed mode. ored with dfs pin internally. cmode, cks1-0: master clock frequency select (see table 1) default: 256fs dif2-0: audio data interface modes (see table 4) 000: mode 0 001: mode 1 010: mode 2 011: mode 3 100: mode 4 default : 24bit msb justified for both adc and dac addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h deem and volume control smute 0 0 0 hpfr hpfl dem1 dem0 default 0 0 0 0 1 1 0 0 dem1-0: de-emphasis response (see table 6) 00: 44.1khz 01: off 10: 48khz 11: 32khz default : 44.1khz. ored with dem1, dem0 pins respectively. hpfr: right channel digital high pass filter control 0: disable 1: enable default : enable hpfl: left channel digital high pass filter control 0: disable 1: enable default : enable smute: dac input soft mute control 0: normal operation 1: dac outputs soft-muted the soft mute is independent of the output att and performed digitally.
[ak4528] ms0011-e-02 2012/01 - 22 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h lch oatt control 0 attl6 a ttl5 attl4 attl3 attl2 attl1 attl0 05h rch oatt control 0 attr6 a ttr5 attr4 attr3 attr2 attr1 attr0 default 0 1 1 1 1 1 1 1 attl/r6-0: dac att level (see table 8) default : 7fh (0db) the oatts are set to ?00h? when pdn pin goes ?l?. after returning to ?h?, the oatts fade in the initial value, ?7fh? by 8031 cycles. the oatts are set to ?00h? when pwda goes ?0?. after returning to ?1?, the oatts fade in the current value. the oa tts are set to ?00h? when rstdan goes ?0?. afer returning to ?1?, the oatts fade in the current value. figure 10. att characteristics -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 127 111 95 79 63 47 31 15 input data(level) att(db) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 step(db) step (db) att (db)
[ak4528] ms0011-e-02 2012/01 - 23 - data internal (datt) gain (db) step width (db) 127 8031 0 - 126 7775 ? 0.28 0.28 125 7519 ? 0.57 0.29 : : : : 112 4191 ? 5.65 0.51 111 3999 ? 6.06 0.41 110 3871 ? 6.34 0.28 : : : : 96 2079 ? 11.74 0.52 95 1983 ? 12.15 0.41 94 1919 ? 12.43 0.28 : : : : 80 1023 ? 17.90 0.53 79 975 ? 18.32 0.42 78 943 ? 18.61 0.29 : : : : 64 495 ? 24.20 0.54 63 471 ? 24.64 0.43 62 455 ? 24.94 0.30 : : : : 48 231 ? 30.82 0.58 47 219 ? 31.29 0.46 46 211 ? 31.61 0.32 : : : : 32 99 ? 38.18 0.67 31 93 ? 38.73 0.54 30 89 ? 39.11 0.38 : : : : 16 33 ? 47.73 0.99 15 30 ? 48.55 0.83 14 28 ? 49.15 0.60 : : : : 5 10 ? 58.10 1.58 4 8 ? 60.03 1.94 3 6 ? 62.53 2.50 2 4 ? 66.05 3.52 1 2 ? 72.07 6.02 0 0 mute oatt external 128 levels are converted to internal 8032 linear levels of datt. internal datt soft-changes between datas. datt=2^m x (2 x l + 33) ? 33 m: msb 3-bits of data l: lsb 4-bits of data table 8. oatt code table
[ak4528] ms0011-e-02 2012/01 - 24 - system design figure 11 shows the system connection diagram. an evaluation board (akd4528) is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. + 4.75 5.25v a nalog supply 10u 2.2u 0.1u 0.1u 0.1u 0.1u 5 rch out lch out 2.7 5.25v digital supply mode setting a udio controller rch lpf lch lpf vcom a inr+ vref a gnd va p/s mclk lrck bick sdto sdti cdti/cks0 cclk/cks1 csn/dif dfs dem1 vt vd dgnd a outl- a outl+ a outr- a outr+ pdn dem0 1 2 3 5 6 7 8 9 11 12 13 14 15 16 17 18 19 20 21 24 25 26 27 28 a k4528 + 10 22 23 4 a inr- a inl+ a inl- rch input buffer lch input buffer notes: - agnd and dgnd of ak4528 should be distributed separately from the ground of external controller etc. - when aout+/ ? drives some capacitive load, some resistor should be added in series between aout+/ ? and capacitive load. - all input pins should not be left floating. figure 11. typical connection diagram 1. grounding and power supply decoupling the ak4528 requires careful attention to power supply a nd grounding arrangements. va and vd are usually supplied from analog supply in system. alternatively if va and vd are supplied separately, the power up sequence is taken care. vt is a power supply pin to interface with the external ics and is supplie d from digital supply in system. agnd and dgnd of the ak4528 should be connected to analog ground plane. system analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as near to the ak4528 as possible, with the small value ceramic capacitor being the nearest.
[ak4528] ms0011-e-02 2012/01 - 25 - 2. voltage reference the differential voltage between vref and agnd sets the an alog input/output range. vref pin is normally connected to va with a 0.1f ceramic capacitor. vcom is a signal ground of this chip. an electrolytic capacitor 2.2f parallel with a 0.1f ceramic capacitor attached to vc om pin eliminates the effects of high frequency noise. no load current may be drawn from vcom pin. all signals, especially clocks, should be kept away from the vref and vcom pins in order to avoid unwanted coupling into the ak4528. 3. analog inputs the ipga inputs are single-ended and the input resistance 27k (typ. @fs=44.1khz). the input signal range scales with the vref voltage and nominally 0.56 x vref vpp. it is recommended that the input dc bias voltage is 0.56va 0.60va as centered in the internal common voltage a bout va/2). the ak4528 can accept input voltages from agnd to va. the adc output data format is 2? s complement. the output code is 7fffffh (@24bit) for input above a positive full scale and 800000h(@24bit) for input below a negative fill s cale. the ideal code is 000000h(@24bit) with no input signal. the dc offset including adc own dc offset removed by the internal hpf (fc=0.9hz@fs=44.1khz). the ak4528 samples the analog inputs at 64fs. the digital f ilter rejects noise above the stopband except for multiples of 64fs. a simple rc filter may be used to attenuate any noi se around 64fs though most audio si gnals do not have significant energy at 64fs. figure 12 is an example of differential input circuit. a k4528 1.5nf 330 + vop+/-=+/-15v signal 10k 330 0.1 22 4.7k 4.7k 5.96vpp 2.8vpp 2 3 4 5 a inr+ a inr- a inl- a inl+ 4.7k vop+ 4.7k va 3.3k 10 bias same circuit 2.8vpp njm5532 + + - - vop- va=5v input rc filter response : fc = 160khz, g = -0.07db at 20khz, -0.26db at 40khz. figure 12. differential input buffer example
[ak4528] ms0011-e-02 2012/01 - 26 - 4. analog outputs the analog outputs are full differential outputs and nominally 0.54 x vref vpp centered in the internal common voltage (about va/2). the differential outputs are summed externally, vout=(aout+) ? (aout ? ) between aout+ and aout ? . if the summing gain is 1, the output range is 5.4vpp (typ@vref=5v). the bias voltage of the external summing circuit is supplied externally. the input data format is 2?s complement. the output voltage is a positive full scale for 7fffffh(@24bit) and a negative full scale for 800000h (@24bit). the ideal aout is 0v for 000000h(@24bit). the internal switched-capacitor filter and the external lpf attenuate the noise ge nerated by the delta-sigma modulator beyond the audio passband. differential outputs can eliminate any dc offset on analog outputs without using capacitors. figure 13 to figure 15 show the example of external op-amp circuit summing the differential outputs. a out- a out+ bias vop vop analog out 4.7k 4.7k r1 4.7k 3300p r1 4.7k 470p 470p 1k 1k 0.1 47 when r1=200ohm fc=93.2khz, q=0.712, g=-0.1db at 40khz when r1=180ohm fc=98.2khz, q=0.681, g=-0.2db at 40khz + - + figure 13. external 2nd order lpf example (using single supply op-amp)
[ak4528] ms0011-e-02 2012/01 - 27 - a out- a out+ +vop -vop analog out 4.7k 4.7k r1 4.7k 3300p r1 4.7k 470p 470p when r1=200ohm fc=93.2khz, q=0.712, g=-0.1db at 40khz when r1=180ohm fc=98.2khz, q=0.681, g=-0.2db at 40khz + - figure 14. external 2nd order lpf example (using dual supply op-amp) a out- a out+ +vop -vop analog out 4.7k 4.7k 4.7k 4.7k 180p 180p fc=188khz + - figure 15. external low cost 1st order lpf example (using dual supply op-amp) ? peripheral i/f example the digital inputs of the ak4528 are ttl inputs and can accept the signal of device with a nominal 3v supply. the digital output can interface with the pe ripheral device with a nominal 3v suppl y when the vt supply operates at a nominal 3v supply. 5v analog 3v digital 3 or 5v digital digital a nalog i/f a udio signal dsp up & others control signal ak4528 figure 16. power supply connection example
[ak4528] ms0011-e-02 2012/01 - 28 - package 1.30 0.1 0.1 0-8 detail a seating plane note: dimension "*" does not include mold flash. 0.10 0.220.05 0.32 0.08 0.65 10.40max 2.1max a 1 14 15 28 28pin ssop (unit: mm) 5.30 7.90 0.20 0.60 0.15 ? package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder plate
[ak4528] ms0011-e-02 2012/01 - 29 - marking AK4528VM xxxbyyyyc xxxbyyyyc: date code identifier xxxb: lot number (x: digit num ber, b: alpha character) yyyyc: assembly date (y: digit number, c: alpha character) date (y/m/d) revision reason page contents 00/01/24 00 first edition 03/01/07 01 error correction 7 filter characteristics adc passband: 22.20 20.20 12/01/12 02 specification change 1, 3, 28, 29 ak4528vf was deleted. (28pin vsop) AK4528VM was added. (28pin ssop) ordering guide was changed. package was changed. marking was changed. revision history
[ak4528] ms0011-e-02 2012/01 - 30 - important notice z these products and their specifications are subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application exampl es of the semiconductor products. you are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your e quipments. akm assumes no responsibility fo r any losses incurred by you or third parties arising from the use of these information herein. akm assumes no liability for infringement of any patent, intellectual property, or other rights in the applica tion or use of such information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of e xport pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor aut horized for use as critical components note1 ) in any safety, life support, or other hazard related device or system note2 ) , and akm assumes no responsibility fo r such use, except for the use approved with the express written consent by representative director of akm. as used here: note1 ) a critical component is one whose failure to functi on or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2 ) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aeros pace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm products , who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above conten t and conditions, and the buyer or distributor agrees to assume any and all responsib ility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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